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W185
Six Output Peak Reducing EMI Solution
Features
* Cypress PREMISTM family offering * Generates an EMI optimized clocking signal at the output * Selectable output frequency range * Six 1.25%, 3.75%, or 0% down or center spread outputs * One non-Spread output of Reference input * Integrated loop filter components * Operates with a 3.3V or 5V supply * Low power CMOS design * Available in 24-pin SSOP (Shrink Small Outline Package) * Outputs may be selectively disabled Table 1. Modulation Width Selection SS% 0 1 W185 Output Fin Fout Fin - 1.25% Fin Fout Fin - 3.75% W185-5 Output Fin + 0.625% Fin - 0.625% Fin + 1.875% Fin -1.875%
Table 2. Frequency Range Selection FS2 0 0 1 FS1 0 1 0 1 Frequency Range 28 MHz FIN 38 MHz 38 MHz FIN 48 MHz 46 MHz FIN 60 MHz 58 MHz FIN 75 MHz
Key Specifications
Supply Voltages: ........................................... VDD = 3.3V5% or VDD = 5V10% Frequency Range: ............................ 28 MHz Fin 75 MHz Crystal Reference Range:................. 28 MHz Fin 40 MHz Cycle to Cycle Jitter: ....................................... 300 ps (max.) Selectable Spread Percentage: ....................1.25% or 3.75% Output Duty Cycle: ............................... 40/60% (worst case) Output Rise and Fall Time: .................................. 5 ns (max.)
1
Table 3. Output Enable EN1 0 0 1 1 EN2 0 1 0 1 Low Low Active Active CLK0:4 Low Active Low Active CLK5
Simplified Block Diagram
3.3V or 5.0V
Pin Configuration
SSOP
X1 XTAL Input
40MHz max.
X2
W185
Spread Spectrum Output (EMI suppressed)
REFOUT FS2 X1 X2 GND SS% EN2 GND CLK0 VDD CLK1 CLK2
1 2 3 4 5 6
24 23 22 21 20 19 18 17 16 15 14 13
SSON# RESET FS1 VDD VDD NC EN1 CLK5 VDD CLK4 GND CLK3
W185/W185-5
7
8 9
3.3V or 5.0V
10
11
12
Oscillator or Reference Input
W185
Spread Spectrum Output (EMI suppressed)
PREMIS is a trademark of Cypress Semiconductor Corporation.
Cypress Semiconductor Corporation
*
3901 North First Street
*
San Jose
*
CA 95134
* 408-943-2600 July 25, 2000, rev. *A
W185
Pin Definitions
Pin Name CLK0:5 CLKIN or X1 Pin No. 9, 11, 12, 13, 15, 17 3 Pin Type O I Pin Description Modulated Frequency Outputs: Frequency modulated copies of the unmodulated input clock (SSON# asserted). Crystal Connection or External Reference Frequency Input: This pin has dual functions. It may either be connected to an external crystal, or to an external reference clock. Crystal Connection: If using an external reference, this pin must be left unconnected. Modulation Width Selection: When Spread Spectrum feature is turned on, this pin is used to select the amount of variation and peak EMI reduction that is desired on the output signal. This pin has an internal pull-up resistor. Modulation Profile Restart: A rising edge on this input restarts the modulation pattern at the beginning of its defined path. This pin has an internal pull-down resistor. Non-Modulated Output: This pin provides a copy of the reference frequency. This output will not have the Spread Spectrum feature enabled regardless of the state of logic input SSON#. Output Enable Select Pins: These pins control the activity of specific output buffers. See Table 3 on page 1. Spread Spectrum Control (Active LOW): Asserting this signal (active LOW) turns the internal modulation waveform on. This pin has an internal pull-down resistor. Frequency Selection Bit 1 and 2: These pins select the frequency of operation. Refer to Table 1. These pins have internal pull-up resistors. Power Connection: Connected to 3.3V or 5V power supply. Ground Connection: This should be connected to the common ground plane. No Connect: This pin should be left floating.
NC or X2 SS%
4 6
I I
Reset
23
I
REFOUT
1
O
EN1:2 SSON#
18, 7 24
I I
FS1:2 VDD GND NC
22, 2 10, 16, 20, 21 5, 8, 14 19
I P G NC
2
W185
Overview
The W185 products are one series of devices in the Cypress PREMIS family. The PREMIS family incorporates the latest advances in PLL spread spectrum frequency synthesizer techniques. By frequency modulating the output with a low-frequency carrier, peak EMI is greatly reduced. Use of this technology allows systems to pass increasingly difficult EMI testing without resorting to costly shielding or redesign. In a system, not only is EMI reduced in the various clock lines, but also in all signals which are synchronized to the clock. Therefore, the benefits of using this technology increase with the number of address and data lines in the system. The Simplified Block Diagram shows a simple implementation. times the reference frequency. (Note: For the W184 the output frequency is nominally equal to the input frequency.) The unique feature of the Spread Spectrum Frequency Timing Generator is that a modulating waveform is superimposed at the input to the VCO. This causes the VCO output to be slowly swept across a predetermined frequency band. Because the modulating frequency is typically 1000 times slower than the fundamental clock, the spread spectrum process has little impact on system performance. Frequency Selection With SSFTG In Spread Spectrum Frequency Timing Generation, EMI reduction depends on the shape, modulation percentage, and frequency of the modulating waveform. While the shape and frequency of the modulating waveform are fixed for a given frequency, the modulation percentage may be varied. Using frequency select bits (FS1:2 pins), the frequency range can be set. Spreading percentage may be selected as either 1.25% or 3.75% (see Table 1). A larger spreading percentage improves EMI reduction. However, large spread percentages may either exceed system maximum frequency ratings or lower the average frequency to a point where performance is affected. For these reasons, spreading percentage options are provided.
Functional Description
The W185 uses a Phase-Locked Loop (PLL) to frequency modulate an input clock. The result is an output clock whose frequency is slowly swept over a narrow band near the input signal. The basic circuit topology is shown in Figure 1. The input reference signal is divided by Q and fed to the phase detector. A signal from the VCO is divided by P and fed back to the phase detector also. The PLL will force the frequency of the VCO output signal to change until the divided output signal and the divided reference signal match at the phase detector input. The output frequency is then equal to the ratio of P/Q
VDD
Clock Input Freq. Divider Q Phase Detector Charge Pump
Reference Input
VCO
Post Dividers
CLKOUT (EMI suppressed)
Modulating Waveform Feedback Divider P
PLL
GND
Figure 1. Functional Block Diagram
3
W185
Spread Spectrum Frequency Timing Generation
The device generates a clock that is frequency modulated in order to increase the bandwidth that it occupies. By increasing the bandwidth of the fundamental and its harmonics, the amplitudes of the radiated electromagnetic emissions are reduced. This effect is depicted in )LJXUH . As shown in )LJXUH , a harmonic of a modulated clock has a much lower amplitude than that of an unmodulated signal. The reduction in amplitude is dependent on the harmonic number and the frequency deviation or spread. The equation for the reduction is: dB = 6.5 + 9*log10(P) + 9*log10(F) Where P is the percentage of deviation and F is the frequency in MHz where the reduction is measured. The output clock is modulated with a waveform depicted in )LJXUH . This waveform, as discussed in "Spread Spectrum Clock Generation for the Reduction of Radiated Emissions" by Bush, Fessler, and Hardin produces the maximum reduction in the amplitude of radiated electromagnetic emissions. )LJXUH details the Cypress spreading pattern. Cypress does offer options with more spread and greater EMI reduction. Contact your local Sales representative for details on these devices.
EMI Reduction
SSFTG
Typical Clock
Amplitude (dB)
Amplitude (dB)
Spread Spectrum Enabled
NonSpread Spectrum
Frequency Span (MHz) Center Spread
Frequency Span (MHz) Down Spread
Figure 2. Clock Harmonic with and without SSCG Modulation Frequency Domain Representation
MAX.
FREQUENCY
10%
20%
30%
40%
50%
60%
70%
80%
90%
100%
10%
20%
30%
40%
50%
60%
70%
80%
90%
MIN.
Figure 3. Typical Modulation Profile
4
100%
W185
Absolute Maximum Ratings
Stresses greater than those listed in this table may cause permanent damage to the device. These represent a stress rating only. Operation of the device at these or any other conditions
.
above those specified in the operating sections of this specification is not implied. Maximum conditions for extended periods may affect reliability. Rating -0.5 to +7.0 -65 to +150 0 to +70 -55 to +125 0.5 Unit V C C C W
Parameter VDD, VIN TSTG TA TB PD
Description Voltage on any pin with respect to GND Storage Temperature Operating Temperature Ambient Temperature under Bias Power Dissipation
DC Electrical Characteristics: 0C < TA < 70C, VDD = 3.3V 5%
Parameter IDD tON VIL VIH VOL VOH IIL IIH IOL IOH CI RP ZOUT Description Supply Current Power Up Time Input Low Voltage Input High Voltage Output Low Voltage Output High Voltage Input Low Current Input High Current Output Low Current Output High Current Input Capacitance Input Pull-Up Resistor Clock Output Impedance 500 25 Note 1 Note 1 @ 0.4V, VDD = 3.3V @ 2.4V, VDD = 3.3V 15 15 7 2.4 -50 50 2.4 0.4 First locked clock cycle after Power Good Test Condition Min. Typ. 18 Max. 32 5 0.8 Unit mA ms V V V V A A mA mA pF k
Note: 1. Inputs FS1:2 have a pull-up resistor; Input SSON# has a pull-down resistor.
5
W185
DC Electrical Characteristics: 0C < TA < 70C, VDD = 5V 10%
Parameter IDD tON VIL VIH VOL VOH IIL IIH IOL IOH CI RP ZOUT Description Supply Current Power Up Time Input Low Voltage Input High Voltage Output Low Voltage Output High Voltage Input Low Current Input High Current Output Low Current Output High Current Input Capacitance Input Pull-Up Resistor Clock Output Impedance 500 25 Note 1 Note 1 @ 0.4V, VDD = 5V @ 2.4V, VDD = 5V 24 24 7 2.4 -100 50 0.7VDD 0.4 First locked clock cycle after Power Good Test Condition Min. Typ. 30 Max. 50 5 0.15VDD Unit mA ms V V V V A A mA mA pF k
AC Electrical Characteristics: TA = 0C to +70C, VDD = 3.3V 5% or 5V10%
Symbol fOSC fIN fOUT tR tF tOD tID tJCYC EMIRED Parameter Internal Xtal Oscillator Frequency Input Frequency Output Frequency Output Rise Time Output Fall Time Output Duty Cycle Input Duty Cycle Jitter, Cycle-to-Cycle Harmonic Reduction fout = 40 MHz, third harmonic measured, reference board, 15-pF load 8 Test Condition Xtal connected to X1, X2 External reference Spread Off, FS2:1 per Table 2 15-pF load 0.8V-2.4V 15-pF load 2.4 -0.8V 15-pF load 40 40 250 Min. 28 28 28 2 2 Typ. Max. 40 75 75 5 5 60 60 300 Unit MHz MHz MHz ns ns % % ps dB
tSK
Output to Output Skew
300
ps
6
W185
Application Information
Recommended Circuit Configuration For optimum performance in system applications the power supply decoupling scheme shown in Figure 4 should be used. VDD decoupling is important to both reduce phase jitter and EMI radiation. The 0.1-F decoupling capacitor should be placed as close to the VDD pin as possible, otherwise the inR Reference Output Logic Input XTAL Connection or Reference Input XTAL Connection or NC
creased trace inductance will negate its decoupling capability. The 10-F decoupling capacitor shown should be a tantalum type. For further EMI protection, the VDD connection can be made via a ferrite bead, as shown. Recommended Board Layout Figure 5 shows a recommended 2-layer board layout.
1 2 3 4 5 6 7 8 9 10 11 12 W185
24 23 22 21 20 19 18 17 16 15 14 13
C2 0.1 F
NC Clock Output Clock Output R Clock Output R
C3 0.1 F R
Clock Output Clock Output Clock Output
R R R
C4 0.1 F
C1 0.1 F 3.3V or 5V System Supply
FB
C5 10 F Tantalum
Figure 4. Recommended Circuit Configuration
C1....C4 = High frequency supply decoupling capacitor (0.1-F recommended).
Xtal Connection or Reference Input
C2 G C3 G
Xtal Connection or NC
C5 = Common supply low frequency decoupling capacitor (10-F tantalum recommended). R = Match value to line impedance FB = Ferrite Bead
G
G
R G Clock Output
R
= Via To GND Plane
C4 G R
C1
G R G
G
Power Supply Input (3.3V or 5V) FB
C5
Figure 5. Recommended Board Layout (2-Layer Board)
Ordering Information
Ordering Code W185 W185-5 Document #: 38-00809-A 7 Package Name H Package Type 24-Pin SSOP (209-mil)
W185
Package Diagram
24-Pin Shrink Small Outline Package (SSOP, 209-mil)
8 7 6 5 4 3
REV .
2
DE S CRIPTIO N
1
DA TE OR IG INA TO R
00
1.00 D/2 1.00 DIA.
3 2 1
INITIAL RELEASE PER DCN#A33907. REVISED PER DCN#D20214. REVISED PER DCN#D20760. REVISED PER DCN#D21151. REVISED PER DCN#D22219. REVISED PER DCN#P60056.
b1 WITH LEAD FINISH
E
2.36 DIA. PIN
01 02 03 04
H+ 1.00
0.20
ME
M E/2
05
HI L I PP
06/13 1991 11/05 1992 11/08 1993 04/26 1994 06/19 1995 03/19 1996
HJC YMK EBA EBA EBA J.B.C. E
E IN
c c1
D
N
6
TOP VIEW
12-16 + e 0.12 b8 A A2 MT E D S
BOTTOM VIEW
C
-C-
-T-
3 0.076 C 7 -E-
-D4
A1
SEATING PLANE .235 MIN
SEE DETAIL "A"
SIDE VIEW B
0 MIN.
END VIEW
GAUGE PLANE PARTING LINE R
G
0.25 BSC C O C L
G A
5 SEATING PLANE L1
DETAIL 'A'
FINIS H
8
7
6
5
8
7
6
5
THIS TABLE IN MILLIMETERS
E
S Y M B O L
COMMON DIMENSIONS NOM. MIN. MAX.
1.86 1.73 0.05 0.13 1.68 1.73 0.25 0.25 0.30 0.09 0.09 0.15 SEE VARIATIONS 5.20 5.30 0.65 BSC 7.65 7.80 0.63 0.75 1.25 REF. SEE VARIATIONS 1.99 0.21 1.78 0.38 0.33 0.20 0.16 5.38 7.90 0.95
N O T E
NOTE VARIATIONS
AA AB AC AD AE AF
D
A A1 A2 b b1 c c1 D E
8,10 10 10 10 4 4
e
H L L1 N
O C
5 6
R
C
0 0.09
4 0.15
8
C
THIS TABLE IN INCHES
S Y M B O L
COMMON DIMENSIONS NOM. MIN. MAX.
.068 .073 .002 .005 .066 .068 .010 .010 .012 .004 .004 .006 SEE VARIATIONS .205 .209 .0256 BSC .301 .307 .025 .030 .049 REF. SEE VARIATIONS .078 .008 .070 .015 .013 .008 .006 .212 .311 .037
N O T E
NOTE VARIATIONS
AA AB AC AD AE AF
B
A A1 A2 b b1 c c1 D E
8,10 10 10 10 4 4
e
H L L1 N
C O
5 6
A
R
0 .004
4 .006
6
8
SIZE
8
7
5
(c) Cypress Semiconductor Corporation, 2000. The information contained herein is subject to change without notice. Cypress Semiconductor Corporation assumes no responsibility for the use of any circuitry other than circuitry embodied in a Cypress Semiconductor product. Nor does it convey or imply any license under patent or other rights. Cypress Semiconductor does not authorize its products for use as critical components in life-support systems where a malfunction or failure may reasonably be expected to result in significant injury to the user. The inclusion of Cypress Semiconductor products in life-support systems application implies that the manufacturer assumes all risk of such use and in doing so indemnifies Cypress Semiconductor against all charges.
S- P
4
D
8.
b BASE METAL
NOTES:
1. 2. 3. 4.
SECTION G-G
10.
MAXIMUM DIE THICKNESS ALLOWABLE IS 0.43mm (.017 INCHES). DIMENSIONING & TOLERANCES PER ANSI.Y14.5M-1982. "T" IS A REFERENCE DATUM. "D" & "E" ARE REFERENCE DATUMS AND DO NOT INCLUDE MOLD FLASH OR PROTRUSIONS, BUT DO INCLUDE MOLD MISMATCH AND ARE MEASURED AT THE PARTING LINE, MOLD FLASH OR PROTRUSIONS SHALL NOT EXCEED 0.15mm PER SIDE. DIMENSION IS THE LENGTH OF TERMINAL FOR SOLDERING TO A SUBSTRATE. TERMINAL POSITIONS ARE SHOWN FOR REFERENCE ONLY. FORMED LEADS SHALL BE PLANAR WITH RESPECT TO ONE ANOTHER WITHIN 0.08mm AT SEATING PLANE. DIMENSION b DOES NOT INCLUDE DAMBAR PROTRUSION/INTRUSION. ALLOWABLE DAMBAR PROTRUSION SHALL BE 0.13mm TOTAL IN EXCESS OF b DIMENSION AT MAXIMUM MATERIAL CONDITION. DAMBAR INTRUSION SHALL NOT REDUCE DIMENSION b BY MORE THAN 0.07mm AT LEAST MATERIAL CONDITION. CONTROLLING DIMENSION: MILLIMETERS.
C
5. 6. 7. 8.
B
9.
10. THESE DIMENSIONS APPLY TO THE FLAT SECTION OF THE LEAD BETWEEN 0.10 AND 0.25mm FROM LEAD TIPS. 11. THIS PACKAGE OUTLINE DRAWING COMPLIES WITH JEDEC SPECIFICATION NO. MO-150 FOR THE LEAD COUNTS SHOWN
DECIMAL XX XXX XXXX
MA TE RIAL
ANGULAR
P RO JEC TION
An a m In du stria l Co ., LT D. Am kor/A na m P ilip in as, INC. Se o ul, K ore a Ma nil a, Ph ili pp ine s Am kor E le ctron ics Am kor E le ctr on ics Ir ving , TX Cha nd le r, AZ D ATE 6 /1 3 19 91 6 /1 3 19 91 6 /1 3 19 91 6 /1 3 19 91 S IZ E D WG . N O. TITL E
E X CE LL EN CE IN S EM IC ON DUCTO R A S SE MB L Y A ND TE ST
A PP RO V AL S DR AW N
M. CHAVEZ
CH ECK E D
PACKAGE OUTLINE, 5.30mm (.209") BODY, SSOP
RE V.
A
M. BANGLOY
E NG 'R
H. BAUTISTA
RE L EA S ED
A1
S CAL E
32289
SHE E T
05 1 of 2
1
DO NOT SCALE DRAWING
H.J. CHOI
4
3
2
4
3
2
1
MIN.
6.07 6.07 7.07 8.07 10.07 10.07
4 D NOM.
6.20 6.20 7.20 8.20 10.20 10.20
6 N MAX.
6.33 6.33 7.33 8.33 10.33 10.33 14 16 20 24 28 30
E
D
VARIATION AF IS DESIGNED BUT NOT TOOLED
MIN.
.239 .239 .278 .318 .397 .397
4 D NOM.
.244 .244 .284 .323 .402 .402
6 N MAX.
.249 .249 .289 .328 .407 .407 14 16 20 24 28 30
B
TITLE
PACKAGE OUTLINE, 5.30mm (.209") BODY, SSOP
DWG. NO. REV.
A
A1
SCALE
32289 8/1
2
SHEET
05 2 of 2
1
4
3

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